Implementation of multiplier based on vertical and crosswire algorithm using kogge stone adder

Priscilla Jennifer. J, Sivasankari. Y, Shalini. R , Sathya. R and G.Sivajanane

Multipliers play a very important role in today’s arithmetic operations. The existing 8X8 multiplier architecture using Vertical and Crosswire Algorithm consists of 4X4 multipliers along with ripple carry adder for addition. The ripple carry adder poses challenge in terms of propagation delay due to its consecutive addition. This project ensures reduction in propagation delay in comparison with the existing multiplier architecture. We are proposing an architecture which makes use of Kogge stone adder instead of carry ripple adder reduces the delay of the multiplier to a further extent. The architecture is to be modelled using VHDL (Very High speed integrated circuit Hardware Description Language) in Altera Quartus II software environment and implemented in Altera Acex FPGA. This multiplier finds application in Digital Signal Processing (DSP) and in Arithmetic and Logic Unit (ALU) of microprocessor and microcontrollers.